As semiconductor devices become smaller, it becomes necessary to arrange individual components within a device such that minimal separation distances are achieved. The need to design compact component arrangements occurs most significantly in memory devices. Because of the large number of components needed to fabricate a typical dynamic-random-access-memory device (DRAM), or static-random-access-memory device (SRAM), the components must be arranged compactly if the overall device dimensions are not to become excessively large. This problem is especially critical in SRAM devices where a typical individual memory cell contains as many as six separate components.
One technique for reducing memory cell dimensions is to place a number of the components in a trench structure, which is sunk into the substrate. Components, such as resistors, capacitors, transistors, and the like, are packed into the trench leaving the remaining active surface area of the cell available for the formation of additional memory cell components. However, as memory devices continue to become more and more complex, there is a need to further reduce the size of the trench itself. This is necessary to allow the placement of even more memory cells in a given area of substrate surface. Because components such as transistors have a certain minimum number of functional components, i.e. a gate electrode, a source and drain region, and the like, new design techniques are needed to pack these components into an even smaller trench.
Even with careful component design and the integration of a trench structure into the memory cell, additional surface area is still necessary for remaining components. For example, active surface regions of the cell must be made available for the interconnection of leads providing supply and ground voltages to the cell. Simple down-sizing of interconnect components can only be pursued to the limit of the line-width definition capability of the manufacturing process. Once the line-width definition limits are reached, new design methodology must be employed if further reduction in memory cell area is to be achieved. Accordingly, a need existed for a new cell design which maximizes the utilization of available space inside the trench, and further reduces the amount of active surface area necessary for the formation of a ULSI semiconductor memory device.